I am a Ph.D. student in the Department of Electrical and Computer Engineering at Sungkyunkwan University, advised by Prof. Jong Hwan Ko.

My research focuses on hardware–software co-design for memory-centric AI systems, with a particular emphasis on processing-in-memory (PIM) architectures. I study performance and reliability challenges in PIM-based systems for emerging AI workloads and develop cross-layer solutions spanning computer architecture, runtime systems, and AI models.

My work has covered SRAM- and DRAM-based PIM systems and has recently expanded to HBM-PIM platforms for efficient and reliable large language model (LLM) inference. Looking ahead, I aim to develop memory-centric AI systems across diverse platforms, from LPDDR-PIM for edge AI to high-bandwidth flash (HBF)-based architectures for large-scale AI inference.

📖 Education

  • 2023.03 - Present, Ph.D. in Electrical and Computer Engineering, Sungkyunkwan University.
  • 2012.03 - 2015.08, B.S. in Electronic and Electrical Engineering, Sungkyunkwan University.

💻 Experience

  • 2025.07 - Present, Visiting Researcher, CEI Lab, Duke University (advisor: Prof. Yiran Chen).
  • 2022.09 - Present, Research Assistant, IRIS Lab, Sungkyunkwan University.
  • 2019.12 - 2022.09, System Software Engineer, Systems Team, Electronics Division, Seoul Metro.
  • 2015.07 - 2018.12, DRAM Development Quality Assurance Engineer, Quality Assurance (QA) Group, Memory Business, Samsung Electronics.

🏆 Honors and Awards

  • 2025.09, 2025 President’s List, Sungkyunkwan University.
  • 2024.09, Best Paper Award, The 31st Korean Conference on Semiconductors (KCS).
  • 2024.07, Grand Prize at the Exynos AI Challenger, Samsung Electronics’ S.LSI. (Team IRIS)
  • 2023.07, Best Paper Award (Top Award), Korean Artificial Intelligence Association (KAIA).
  • 2023-2025, Graduate Excellence Scholarship Recipient, Sungkyunkwan University.
  • 2015.08, Dean’s List Award, Sungkyunkwan University.
  • 2014.02, Qualcomm Scholarship Recipient, Qualcomm (Korea).

📝 Publications

Selected Publications

[1] DAC 2026 Juhong Park, Yintao He, Sangheum Yeon, Yiran Chen, and Jong Hwan Ko; REFLEX: Rewrite-Free Row-Aligned Sparse Attention for Efficient LLM Execution on PIM. In ACM/IEEE Design Automation Conference (DAC), 2026.

[2] JSA 2025 Juhong Park, Johnny Rhe, Chanwook Hwang, Jaehyeon So, and Jong Hwan Ko; Input/Mapping Precision Controllable Digital CIM with Adaptive Adder Tree Architecture for Flexible DNN Inference. In Journal of Systems Architecture (JSA), 2025. (JCR Q1)

[3] ICCE-Asia 2024 Juhong Park and Jong Hwan Ko; Fully Approximate Computing for Efficient Multi-Bit DNN Inference in CIM Arrays. In IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia), 2024.

[4] ISOCC 2024 Juhong Park and Jong Hwan Ko; C-afa: A Conditionally Approximate Full Adder for Efficient DNN Inference in CIM Arrays. In International SoC Design Conference (ISOCC), 2024.

[5] ISCAS 2024 Juhong Park, Johnny Rhe, and Jong Hwan Ko; KARS: Kernel-Grouping Aided Row-Skipping for SDK-based Weight Compression in PIM Arrays. In IEEE International Symposium on Circuits and Systems (ISCAS), 2024.

Collaborative Publications

[6] ISLPED 2026 Yeong Hwan Oh, Do Yeong Kang, Juhong Park, Chanwook Hwang, Kang Eun Jeon, and Jong Hwan Ko; HyperSPACE: Sparse-Adder-Compatible Encoding for Efficient Hyperdimensional Computing on Digital CIM Arrays. In IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2026.

[7] APCCAS 2025 Johnny Rhe, Juhong Park, Kang Eun Jeon, and Jong Hwan Ko; ETA: Efficient Transformer Attention Mapping for ReRAM-based Compute-In-Memory Architectures. In Asia Pacific Conference on Circuits and Systems (APCCAS), 2025.

[8] AICAS 2024 Chanwook Hwang, Jaehyeon So, Johnny Rhe, Jiyoon Kim, Juhong Park, Kang Eun Jeon, and Jong Hwan Ko; An Efficient Ventricular Arrhythmias Detection on Microcontrollers with Optimized 1D CNN. In IEEE Artificial Intelligence Circuits and Systems (AICAS), 2024.